1. Field of Invention
The present invention relates to a self-calibration circuit for capacitance mismatch, and more particularly to an approximation self-calibration circuit for capacitance mismatch.
2. Description of Related Art
In integrated circuits (IC), capacitance match is always one of the important design considerations. In ICs, such as switch-capacitor circuits and digital-to-analog converters (DACs), etc., the performance of the circuits might be restricted due to capacitance mismatch resulting from deviation in the manufacturing process, such that the circuit cannot achieve the level of the original design. Therefore, with IC design, how to compensate the capacitance mismatch caused by deviation in the manufacturing process so as to enable the designed circuit to achieve the original performance and precision is a critical consideration.
In the conventional art, an additional capacitor array formed by connecting the original capacitors in parallel is generally utilized to compensate the capacitance mismatch. After the IC is formed, the designer measures the transfer function of the circuit output to determine the amount of capacitance mismatch/deviation, then the capacitor array connected in parallel is cut and removed one by one using the method of laser trim, or the capacitor array connected in parallel is connected and attached one by one using the method of focused ion beam (FIB), until the transfer function of the circuit output is finally the same as a predetermined desired value, i.e. the capacitance reaches a matched result. However, regardless whether laser trim or FIB, additional manual resources are required to measure and calibrate the chipped ICs, and it will cost additional expenditure and a great deal of time, thus the manufacturing cost will be increased. Therefore, if the work of calibration compensation for capacitance mismatch can be integrated into the IC to achieve the effect of self-calibration, it would be a great help for IC design.
Taiwan Patent Application No. 92133509 discloses a self-calibration circuit as shown in FIG. 1, wherein a plurality of analog voltages are outputted to a sample and hold (S/H) and shift circuit 102 in sequence through a DAC 104; and then the input voltage is compared with the previous voltage by a comparator 100, to determine whether or not the selector 108 is used to compensate the capacitance of the DAC 104. The control of the compensation capacitance is determined by the counters 111–113. The disadvantages of the method are as follows:
First, an S/H and shift circuit 102 comprising an S/H circuit and a real-time switching circuit is required for the original design, which increases the complexity of the circuit design.
Second, a plurality of analog voltages corresponding to digital codes should be generated by the DAC 104 for comparison, and the voltage source and the precision of this design are problematic. Moreover, the circuit design is very complicated.
Third, repeated modification steps for each of the digital codes are needed in this method, thus the clock operation time required is quite long, and the hardware area of the digital circuit is very large.